PIC16F873T-04E/SO【PDF 158/218 页】IC MCU FLASH 4KX14 EE 28SOIC

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PIC16F87X

DS30292C-page 42

2001 Microchip Technology Inc.

Write operations have two control bits, WR and WREN,

and two status bits, WRERR and EEIF. The WREN bit

is used to enable or disable the write operation. When

WREN is clear, the write operation will be disabled.

Therefore, the WREN bit must be set before executing

a write operation. The WR bit is used to initiate the write

operation. It also is automatically cleared at the end of

the write operation. The interrupt flag EEIF is used to

determine when the memory write completes. This flag

must be cleared in software before setting the WR bit.

For EEPROM data memory, once the WREN bit and

the WR bit have been set, the desired memory address

in EEADR will be erased, followed by a write of the data

in EEDATA. This operation takes place in parallel with

the microcontroller continuing to execute normally.

When the write is complete, the EEIF flag bit will be set.

For program memory, once the WREN bit and the WR

bit have been set, the microcontroller will cease to exe-

cute instructions. The desired memory location pointed

to by EEADRH:EEADR will be erased. Then, the data

value in EEDATH:EEDATA will be programmed. When

complete, the EEIF flag bit will be set and the microcon-

troller will continue to execute code.

The WRERR bit is used to indicate when the

PIC16F87X device has been reset during a write oper-

ation. WRERR should be cleared after Power-on

Reset. Thereafter, it should be checked on any other

RESET. The WRERR bit is set when a write operation

is interrupted by a MCLR Reset, or a WDT Time-out

Reset, during normal operation. In these situations, fol-

lowing a RESET, the user should check the WRERR bit

and rewrite the memory location, if set. The contents of

the data registers, address registers and EEPGD bit

are not affected by either MCLR Reset, or WDT Time-

out Reset, during normal operation.

REGISTER 4-1:

EECON1 REGISTER (ADDRESS 18Ch)

R/W-x

U-0

R/W-x

R/W-0

R/S-0

EEPGD

—

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: Program/Data EEPROM Select bit

= Accesses program memory

= Accesses data memory

(This bit cannot be changed while a read or write operation is in progress)

bit 6-4

Unimplemented: Read as '0'

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR Reset or any WDT Reset during normal operation)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the EEPROM

bit 1

WR: Write Control bit

= Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not

cleared) in software.)

= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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